41.
Bagherzadeh, Mojtaba; Bordeleau, Francis; Bruel, Jean-Michel; Dingel, Juergen; Gerard, Sebastien; Hili, Nicolas; Voss, Sebastian
Summary of Workshop on Model-Driven Engineering Tools (MDETools'17) Inproceedings
In: MODELS 2017 Satellite Events Proceedings, pp. 336-337, Austin, Texas, USA, 2017.
@inproceedings{BBBDGHV18b,
title = {Summary of Workshop on Model-Driven Engineering Tools (MDETools'17)},
author = {Mojtaba Bagherzadeh and Francis Bordeleau and Jean-Michel Bruel and Juergen Dingel and Sebastien Gerard and Nicolas Hili and Sebastian Voss},
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42.
Bagherzadeh, Mojtaba; Bordeleau, Francis; Bruel, Jean-Michel; Dingel, Juergen; Gerard, Sebastien; Hili, Nicolas; Voss, Sebastian
Summary of Workshop on Model-Driven Engineering Tools (MDETools'17) Inproceedings
In: MODELS 2017 Satellite Events Proceedings, pp. 336-337, Austin, Texas, USA, 2017.
@inproceedings{BBBDGHV18,
title = {Summary of Workshop on Model-Driven Engineering Tools (MDETools'17)},
author = {Mojtaba Bagherzadeh and Francis Bordeleau and Jean-Michel Bruel and Juergen Dingel and Sebastien Gerard and Nicolas Hili and Sebastian Voss},
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43.
Waez, Md. Tawhid Bin; Wąsowski, Andrzej; Dingel, Juergen; Rudie, Karen
Controller Synthesis for Dynamic Hierarchical Real-Time Plants Using Timed Automata Journal Article
In: Journal Discrete Event Dynamic Systems, Special Issue on Formal Methods in Control, 27 , pp. 407-441, 2017.
@article{WWD+17b,
title = {Controller Synthesis for Dynamic Hierarchical Real-Time Plants Using Timed Automata},
author = {Md. Tawhid Bin Waez and Andrzej Wąsowski and Juergen Dingel and Karen Rudie},
url = {http://dx.doi.org/10.1007/s10626-017-0240-2},
doi = {10.1007/s10626-017-0240-2},
year = {2017},
date = {2017-06-01},
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volume = {27},
pages = {407-441},
publisher = {Springer},
abstract = {We use timed I/O automata based timed games to synthesize task-level reconfiguration services for cost-effective fault tolerance in a case study. The case study shows that state-space explosion is a severe problem for timed games. By applying suitable abstractions, we dramatically improve the scalability. However, timed I/O automata do not facilitate algorithmic abstraction generation techniques. The case study motivates the development of timed process automata to improve modeling and analysis for controller synthesis of time-critical plants which can be hierarchical and dynamic. The model offers two essential features for industrial systems: (i) compositional modeling with reusable designs for different contexts, and (ii) state-space reduction technique. Timed process automata model dynamic networks of continuous-time communicating plant processes which can activate other plant processes. We show how to establish safety and reachability properties of timed process automata by reduction to solving timed games. To mitigate the state-space explosion problem, an algorithmic state-space reduction technique using compositional reasoning and aggressive abstractions is also proposed. In this article, we demonstrate the theoretical framework of timed process automata and the effectiveness of the proposed state-space reduction technique by extending the case study.},
keywords = {},
pubstate = {published},
tppubtype = {article}
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We use timed I/O automata based timed games to synthesize task-level reconfiguration services for cost-effective fault tolerance in a case study. The case study shows that state-space explosion is a severe problem for timed games. By applying suitable abstractions, we dramatically improve the scalability. However, timed I/O automata do not facilitate algorithmic abstraction generation techniques. The case study motivates the development of timed process automata to improve modeling and analysis for controller synthesis of time-critical plants which can be hierarchical and dynamic. The model offers two essential features for industrial systems: (i) compositional modeling with reusable designs for different contexts, and (ii) state-space reduction technique. Timed process automata model dynamic networks of continuous-time communicating plant processes which can activate other plant processes. We show how to establish safety and reachability properties of timed process automata by reduction to solving timed games. To mitigate the state-space explosion problem, an algorithmic state-space reduction technique using compositional reasoning and aggressive abstractions is also proposed. In this article, we demonstrate the theoretical framework of timed process automata and the effectiveness of the proposed state-space reduction technique by extending the case study.
44.
Waez, Md. Tawhid Bin; Wąsowski, Andrzej; Dingel, Juergen; Rudie, Karen
Controller Synthesis for Dynamic Hierarchical Real-Time Plants Using Timed Automata Journal Article
In: Journal Discrete Event Dynamic Systems, Special Issue on Formal Methods in Control, 27 , pp. 407-441, 2017.
@article{WWD+17,
title = {Controller Synthesis for Dynamic Hierarchical Real-Time Plants Using Timed Automata},
author = {Md. Tawhid Bin Waez and Andrzej Wąsowski and Juergen Dingel and Karen Rudie},
url = {http://dx.doi.org/10.1007/s10626-017-0240-2},
doi = {10.1007/s10626-017-0240-2},
year = {2017},
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volume = {27},
pages = {407-441},
publisher = {Springer},
abstract = {We use timed I/O automata based timed games to synthesize task-level reconfiguration services for cost-effective fault tolerance in a case study. The case study shows that state-space explosion is a severe problem for timed games. By applying suitable abstractions, we dramatically improve the scalability. However, timed I/O automata do not facilitate algorithmic abstraction generation techniques. The case study motivates the development of timed process automata to improve modeling and analysis for controller synthesis of time-critical plants which can be hierarchical and dynamic. The model offers two essential features for industrial systems: (i) compositional modeling with reusable designs for different contexts, and (ii) state-space reduction technique. Timed process automata model dynamic networks of continuous-time communicating plant processes which can activate other plant processes. We show how to establish safety and reachability properties of timed process automata by reduction to solving timed games. To mitigate the state-space explosion problem, an algorithmic state-space reduction technique using compositional reasoning and aggressive abstractions is also proposed. In this article, we demonstrate the theoretical framework of timed process automata and the effectiveness of the proposed state-space reduction technique by extending the case study.},
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We use timed I/O automata based timed games to synthesize task-level reconfiguration services for cost-effective fault tolerance in a case study. The case study shows that state-space explosion is a severe problem for timed games. By applying suitable abstractions, we dramatically improve the scalability. However, timed I/O automata do not facilitate algorithmic abstraction generation techniques. The case study motivates the development of timed process automata to improve modeling and analysis for controller synthesis of time-critical plants which can be hierarchical and dynamic. The model offers two essential features for industrial systems: (i) compositional modeling with reusable designs for different contexts, and (ii) state-space reduction technique. Timed process automata model dynamic networks of continuous-time communicating plant processes which can activate other plant processes. We show how to establish safety and reachability properties of timed process automata by reduction to solving timed games. To mitigate the state-space explosion problem, an algorithmic state-space reduction technique using compositional reasoning and aggressive abstractions is also proposed. In this article, we demonstrate the theoretical framework of timed process automata and the effectiveness of the proposed state-space reduction technique by extending the case study.
45.
Bagherzadeh, Mojtaba; Bordeleau, Francis; Bruel, Jean-Michel; Dingel, Juergen; Gerard, Sebastien; Hili, Nicolas; Voss, Sebastian
Summary of Workshop on Model-Driven Engineering Tools (MDETools'17) Inproceedings
In: MODELS 2017 Satellite Events Proceedings, pp. 2, Austin, Texas, USA, 2017, (To appear).
@inproceedings{BBBDGHV17b,
title = {Summary of Workshop on Model-Driven Engineering Tools (MDETools'17)},
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46.
Selim, Gehan M K; Cordy, James R; Dingel, Juergen
How is ATL Really Used? Language Feature Use in the ATL Zoo Inproceedings
In: ACM/IEEE 20th International Conference on Model Driven Engineering Languages and Systems (MODELS 2017), pp. 11 pages, Austin, Texas. Sept 17-22, 2017, 2017.
@inproceedings{SCD17b,
title = {How is ATL Really Used? Language Feature Use in the ATL Zoo},
author = {Gehan M K Selim and James R Cordy and Juergen Dingel},
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47.
Oliveira, Raquel; Dingel, Juergen
Supporting Model Refinement with Equivalence Checking in the Context of Model-Driven Engineering with UML-RT Inproceedings
In: 14th Workshop on Model-driven Engineering, Verification, and Validation (MoDeVVa'17), pp. 7, Austin, Texas. Sept 19, 2017, 2017, (To appear).
@inproceedings{OD17b,
title = {Supporting Model Refinement with Equivalence Checking in the Context of Model-Driven Engineering with UML-RT},
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note = {To appear},
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}
48.
Bagherzadeh, Mojtaba; Kahani, Nafiseh; Bezemer, Cor-Paul; Hassan, Ahmed E; Dingel, Juergen; Cordy, James R
Analyzing a Decade of Linux System Calls Journal Article
In: Empirical Software Engineering Journal, 2017.
@article{BKB+17b,
title = {Analyzing a Decade of Linux System Calls},
author = {Mojtaba Bagherzadeh and Nafiseh Kahani and Cor-Paul Bezemer and Ahmed E Hassan and Juergen Dingel and James R Cordy},
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year = {2017},
date = {2017-01-01},
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49.
Bagherzadeh, Mojtaba; Hili, Nicolas; Dingel, Juergen
Model-Level, Platform-Independent Debugging In The Context Of The Model-Driven Development Of Real-time Systems Inproceedings
In: 11th Joint Meeting of the European Software Engineering Conference and the ACM SIGSOFT Symposium on the Foundations of Software Engineering (ESEC/FSE'17), Paderborn, Germany. September 04-08, 2017, 2017.
@inproceedings{Bhd17b,
title = {Model-Level, Platform-Independent Debugging In The Context Of The Model-Driven Development Of Real-time Systems},
author = {Mojtaba Bagherzadeh and Nicolas Hili and Juergen Dingel},
url = {https://dl.acm.org/citation.cfm?id=3106278, paper
https://github.com/moji1/MDebugger, code},
doi = {10.1145/3106237.3106278},
year = {2017},
date = {2017-01-01},
booktitle = {11th Joint Meeting of the European Software Engineering Conference and the ACM SIGSOFT Symposium on the Foundations of Software Engineering (ESEC/FSE'17)},
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abstract = {Providing proper support for debugging models at model-level is one of the main barriers to a broader adoption of Model Driven Development (MDD). In this paper, we focus on the use of MDD for the development of real-time embedded systems (RTE). We introduce a new platform-independent approach to implement model-level debuggers. We describe how to realize support for model-level debugging entirely in terms of the modeling language and show how to implement this support in terms of a model-to-model transformation. Key advantages of the approach over existing work are that (1) it does not require a program debugger for the code generated from the model, and that (2) any changes to, e.g., the code generator, the target language, or the hardware platform leave the debugger completely unaffected. We also describe an implementation of the approach in the context of Papyrus-RT, an open source MDD tool based on the modeling language UML-RT. We summarize the results of the use of our model-based debugger on several use cases to determine its overhead in terms of size and performance. Despite being a prototype, the performance overhead is in the order of microseconds, while the size overhead is comparable with that of GDB, the GNU Debugger.},
keywords = {},
pubstate = {published},
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}
Providing proper support for debugging models at model-level is one of the main barriers to a broader adoption of Model Driven Development (MDD). In this paper, we focus on the use of MDD for the development of real-time embedded systems (RTE). We introduce a new platform-independent approach to implement model-level debuggers. We describe how to realize support for model-level debugging entirely in terms of the modeling language and show how to implement this support in terms of a model-to-model transformation. Key advantages of the approach over existing work are that (1) it does not require a program debugger for the code generated from the model, and that (2) any changes to, e.g., the code generator, the target language, or the hardware platform leave the debugger completely unaffected. We also describe an implementation of the approach in the context of Papyrus-RT, an open source MDD tool based on the modeling language UML-RT. We summarize the results of the use of our model-based debugger on several use cases to determine its overhead in terms of size and performance. Despite being a prototype, the performance overhead is in the order of microseconds, while the size overhead is comparable with that of GDB, the GNU Debugger.
50.
Hili, Nicolas; Dingel, Juergen; Beaulieu, Alain
Modelling and Code Generation for Real-time Embedded Systems with UML-RT and Papyrus-RT Inproceedings
In: 39th International Conference on Software Engineering Companion, pp. 509–510, IEEE, Buenos Aires, Argentina. May 21-22, 2017, 2017, ISBN: 978-1-5386-1589-8.
@inproceedings{Hili:2017:MCG:3098344.3098520b,
title = {Modelling and Code Generation for Real-time Embedded Systems with UML-RT and Papyrus-RT},
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51.
Kahani, Nafiseh; Hili, Nicolas; Cordy, James R; Dingel, Juergen
Evaluation of UML-RT and Papyrus-RT for Modelling Self-adaptive Systems Inproceedings
In: 9th International Workshop on Modelling in Software Engineering (MiSE'17), pp. 12–18, IEEE, Buenos Aires, Argentina. May 21-22, 2017, 2017, ISBN: 978-1-5386-0426-7.
@inproceedings{Kahani:2017:EUP:3104068.3104074b,
title = {Evaluation of UML-RT and Papyrus-RT for Modelling Self-adaptive Systems},
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52.
Madzar, Boris; Boudjadar, Jalil; Dingel, Juergen; Fuhrman, Thomas E; S., Ramesh
Formal Analysis of Predictable Data Flow in Fault-Tolerant Multicore Systems Inproceedings
In: Kouchnarenko, Olga; Khosravi, Ramtin (Ed.): 13th International Conference on Formal Aspects of Component Software (FACS'16), pp. 153–171, Springer, Besançon, France. October 19-21, 2016, 2017, ISBN: 978-3-319-57666-4.
@inproceedings{Madzar2017b,
title = {Formal Analysis of Predictable Data Flow in Fault-Tolerant Multicore Systems},
author = {Boris Madzar and Jalil Boudjadar and Juergen Dingel and Thomas E Fuhrman and Ramesh S.},
editor = {Olga Kouchnarenko and Ramtin Khosravi},
url = {http://dx.doi.org/10.1007/978-3-319-57666-4_10},
doi = {10.1007/978-3-319-57666-4_10},
isbn = {978-3-319-57666-4},
year = {2017},
date = {2017-01-01},
booktitle = {13th International Conference on Formal Aspects of Component Software (FACS'16)},
pages = {153--171},
publisher = {Springer},
address = {Besançon, France. October 19-21, 2016},
abstract = {The need to integrate large and complex functions into today's vehicle electronic control systems requires high performance computing platforms, while at the same time the manufacturers try to reduce cost, power consumption and ensure safety. Traditionally, safety isolation and fault containment of software tasks have been achieved by either physically or temporally segregating them. This approach is reliable but inefficient in terms of processor utilization. Dynamic approaches that achieve better utilization without sacrificing safety isolation and fault containment appear to be of increasing interest. One of these approaches relies on predictable data flow introduced in PharOS and Giotto. In this paper, we extend the work on leveraging predictable data flow by addressing the problem of how the predictability of data flow can be proved formally for mixed criticality systems that run on multicore platforms and are subject to failures. We consider dynamic tasks where the timing attributes vary from one period to another. Our setting also allows for sporadic deadline overruns and accounts for criticality during fault handling. A user interface was created to allow automatic generation of the models as well as visualization of the analysis results, whereas predictability is verified using the Spin model checker.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
The need to integrate large and complex functions into today's vehicle electronic control systems requires high performance computing platforms, while at the same time the manufacturers try to reduce cost, power consumption and ensure safety. Traditionally, safety isolation and fault containment of software tasks have been achieved by either physically or temporally segregating them. This approach is reliable but inefficient in terms of processor utilization. Dynamic approaches that achieve better utilization without sacrificing safety isolation and fault containment appear to be of increasing interest. One of these approaches relies on predictable data flow introduced in PharOS and Giotto. In this paper, we extend the work on leveraging predictable data flow by addressing the problem of how the predictability of data flow can be proved formally for mixed criticality systems that run on multicore platforms and are subject to failures. We consider dynamic tasks where the timing attributes vary from one period to another. Our setting also allows for sporadic deadline overruns and accounts for criticality during fault handling. A user interface was created to allow automatic generation of the models as well as visualization of the analysis results, whereas predictability is verified using the Spin model checker.
53.
Bagherzadeh, Mojtaba; Bordeleau, Francis; Bruel, Jean-Michel; Dingel, Juergen; Gerard, Sebastien; Hili, Nicolas; Voss, Sebastian
Summary of Workshop on Model-Driven Engineering Tools (MDETools'17) Inproceedings
In: MODELS 2017 Satellite Events Proceedings, pp. 2, Austin, Texas, USA, 2017, (To appear).
@inproceedings{BBBDGHV17,
title = {Summary of Workshop on Model-Driven Engineering Tools (MDETools'17)},
author = {Mojtaba Bagherzadeh and Francis Bordeleau and Jean-Michel Bruel and Juergen Dingel and Sebastien Gerard and Nicolas Hili and Sebastian Voss},
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address = {Austin, Texas, USA},
note = {To appear},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
54.
Selim, Gehan M K; Cordy, James R; Dingel, Juergen
How is ATL Really Used? Language Feature Use in the ATL Zoo Inproceedings
In: ACM/IEEE 20th International Conference on Model Driven Engineering Languages and Systems (MODELS 2017), pp. 11 pages, Austin, Texas. Sept 17-22, 2017, 2017.
@inproceedings{SCD17,
title = {How is ATL Really Used? Language Feature Use in the ATL Zoo},
author = {Gehan M K Selim and James R Cordy and Juergen Dingel},
url = {http://doi.ieeecomputersociety.org/10.1109/MODELS.2017.20},
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address = {Austin, Texas. Sept 17-22, 2017},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
55.
Oliveira, Raquel; Dingel, Juergen
Supporting Model Refinement with Equivalence Checking in the Context of Model-Driven Engineering with UML-RT Inproceedings
In: 14th Workshop on Model-driven Engineering, Verification, and Validation (MoDeVVa'17), pp. 7, Austin, Texas. Sept 19, 2017, 2017, (To appear).
@inproceedings{OD17,
title = {Supporting Model Refinement with Equivalence Checking in the Context of Model-Driven Engineering with UML-RT},
author = {Raquel Oliveira and Juergen Dingel},
year = {2017},
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booktitle = {14th Workshop on Model-driven Engineering, Verification, and Validation (MoDeVVa'17)},
pages = {7},
address = {Austin, Texas. Sept 19, 2017},
note = {To appear},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
56.
Bagherzadeh, Mojtaba; Kahani, Nafiseh; Bezemer, Cor-Paul; Hassan, Ahmed E; Dingel, Juergen; Cordy, James R
Analyzing a Decade of Linux System Calls Journal Article
In: Empirical Software Engineering Journal, 2017.
@article{BKB+17,
title = {Analyzing a Decade of Linux System Calls},
author = {Mojtaba Bagherzadeh and Nafiseh Kahani and Cor-Paul Bezemer and Ahmed E Hassan and Juergen Dingel and James R Cordy},
url = {https://doi.org/10.1007/s10664-017-9551-z},
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year = {2017},
date = {2017-01-01},
journal = {Empirical Software Engineering Journal},
publisher = {Springer},
keywords = {},
pubstate = {published},
tppubtype = {article}
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57.
Bagherzadeh, Mojtaba; Hili, Nicolas; Dingel, Juergen
Model-Level, Platform-Independent Debugging In The Context Of The Model-Driven Development Of Real-time Systems Inproceedings
In: 11th Joint Meeting of the European Software Engineering Conference and the ACM SIGSOFT Symposium on the Foundations of Software Engineering (ESEC/FSE'17), Paderborn, Germany. September 04-08, 2017, 2017.
@inproceedings{Bhd17,
title = {Model-Level, Platform-Independent Debugging In The Context Of The Model-Driven Development Of Real-time Systems},
author = {Mojtaba Bagherzadeh and Nicolas Hili and Juergen Dingel},
url = {https://dl.acm.org/citation.cfm?id=3106278, paper
https://github.com/moji1/MDebugger, code},
doi = {10.1145/3106237.3106278},
year = {2017},
date = {2017-01-01},
booktitle = {11th Joint Meeting of the European Software Engineering Conference and the ACM SIGSOFT Symposium on the Foundations of Software Engineering (ESEC/FSE'17)},
address = {Paderborn, Germany. September 04-08, 2017},
series = {ESEC/FSE'17},
abstract = {Providing proper support for debugging models at model-level is one of the main barriers to a broader adoption of Model Driven Development (MDD). In this paper, we focus on the use of MDD for the development of real-time embedded systems (RTE). We introduce a new platform-independent approach to implement model-level debuggers. We describe how to realize support for model-level debugging entirely in terms of the modeling language and show how to implement this support in terms of a model-to-model transformation. Key advantages of the approach over existing work are that (1) it does not require a program debugger for the code generated from the model, and that (2) any changes to, e.g., the code generator, the target language, or the hardware platform leave the debugger completely unaffected. We also describe an implementation of the approach in the context of Papyrus-RT, an open source MDD tool based on the modeling language UML-RT. We summarize the results of the use of our model-based debugger on several use cases to determine its overhead in terms of size and performance. Despite being a prototype, the performance overhead is in the order of microseconds, while the size overhead is comparable with that of GDB, the GNU Debugger.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Providing proper support for debugging models at model-level is one of the main barriers to a broader adoption of Model Driven Development (MDD). In this paper, we focus on the use of MDD for the development of real-time embedded systems (RTE). We introduce a new platform-independent approach to implement model-level debuggers. We describe how to realize support for model-level debugging entirely in terms of the modeling language and show how to implement this support in terms of a model-to-model transformation. Key advantages of the approach over existing work are that (1) it does not require a program debugger for the code generated from the model, and that (2) any changes to, e.g., the code generator, the target language, or the hardware platform leave the debugger completely unaffected. We also describe an implementation of the approach in the context of Papyrus-RT, an open source MDD tool based on the modeling language UML-RT. We summarize the results of the use of our model-based debugger on several use cases to determine its overhead in terms of size and performance. Despite being a prototype, the performance overhead is in the order of microseconds, while the size overhead is comparable with that of GDB, the GNU Debugger.
58.
Hili, Nicolas; Dingel, Juergen; Beaulieu, Alain
Modelling and Code Generation for Real-time Embedded Systems with UML-RT and Papyrus-RT Inproceedings
In: 39th International Conference on Software Engineering Companion, pp. 509–510, IEEE, Buenos Aires, Argentina. May 21-22, 2017, 2017, ISBN: 978-1-5386-1589-8.
@inproceedings{Hili:2017:MCG:3098344.3098520,
title = {Modelling and Code Generation for Real-time Embedded Systems with UML-RT and Papyrus-RT},
author = {Nicolas Hili and Juergen Dingel and Alain Beaulieu},
url = {https://doi.org/10.1109/ICSE-C.2017.168},
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59.
Kahani, Nafiseh; Hili, Nicolas; Cordy, James R; Dingel, Juergen
Evaluation of UML-RT and Papyrus-RT for Modelling Self-adaptive Systems Inproceedings
In: 9th International Workshop on Modelling in Software Engineering (MiSE'17), pp. 12–18, IEEE, Buenos Aires, Argentina. May 21-22, 2017, 2017, ISBN: 978-1-5386-0426-7.
@inproceedings{Kahani:2017:EUP:3104068.3104074,
title = {Evaluation of UML-RT and Papyrus-RT for Modelling Self-adaptive Systems},
author = {Nafiseh Kahani and Nicolas Hili and James R Cordy and Juergen Dingel},
url = {https://doi.org/10.1109/MiSE.2017..4},
doi = {10.1109/MiSE.2017..4},
isbn = {978-1-5386-0426-7},
year = {2017},
date = {2017-01-01},
booktitle = {9th International Workshop on Modelling in Software Engineering (MiSE'17)},
pages = {12--18},
publisher = {IEEE},
address = {Buenos Aires, Argentina. May 21-22, 2017},
series = {MISE'17},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
60.
Madzar, Boris; Boudjadar, Jalil; Dingel, Juergen; Fuhrman, Thomas E; S., Ramesh
Formal Analysis of Predictable Data Flow in Fault-Tolerant Multicore Systems Inproceedings
In: Kouchnarenko, Olga; Khosravi, Ramtin (Ed.): 13th International Conference on Formal Aspects of Component Software (FACS'16), pp. 153–171, Springer, Besançon, France. October 19-21, 2016, 2017, ISBN: 978-3-319-57666-4.
@inproceedings{Madzar2017,
title = {Formal Analysis of Predictable Data Flow in Fault-Tolerant Multicore Systems},
author = {Boris Madzar and Jalil Boudjadar and Juergen Dingel and Thomas E Fuhrman and Ramesh S.},
editor = {Olga Kouchnarenko and Ramtin Khosravi},
url = {http://dx.doi.org/10.1007/978-3-319-57666-4_10},
doi = {10.1007/978-3-319-57666-4_10},
isbn = {978-3-319-57666-4},
year = {2017},
date = {2017-01-01},
booktitle = {13th International Conference on Formal Aspects of Component Software (FACS'16)},
pages = {153--171},
publisher = {Springer},
address = {Besançon, France. October 19-21, 2016},
abstract = {The need to integrate large and complex functions into today's vehicle electronic control systems requires high performance computing platforms, while at the same time the manufacturers try to reduce cost, power consumption and ensure safety. Traditionally, safety isolation and fault containment of software tasks have been achieved by either physically or temporally segregating them. This approach is reliable but inefficient in terms of processor utilization. Dynamic approaches that achieve better utilization without sacrificing safety isolation and fault containment appear to be of increasing interest. One of these approaches relies on predictable data flow introduced in PharOS and Giotto. In this paper, we extend the work on leveraging predictable data flow by addressing the problem of how the predictability of data flow can be proved formally for mixed criticality systems that run on multicore platforms and are subject to failures. We consider dynamic tasks where the timing attributes vary from one period to another. Our setting also allows for sporadic deadline overruns and accounts for criticality during fault handling. A user interface was created to allow automatic generation of the models as well as visualization of the analysis results, whereas predictability is verified using the Spin model checker.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
The need to integrate large and complex functions into today's vehicle electronic control systems requires high performance computing platforms, while at the same time the manufacturers try to reduce cost, power consumption and ensure safety. Traditionally, safety isolation and fault containment of software tasks have been achieved by either physically or temporally segregating them. This approach is reliable but inefficient in terms of processor utilization. Dynamic approaches that achieve better utilization without sacrificing safety isolation and fault containment appear to be of increasing interest. One of these approaches relies on predictable data flow introduced in PharOS and Giotto. In this paper, we extend the work on leveraging predictable data flow by addressing the problem of how the predictability of data flow can be proved formally for mixed criticality systems that run on multicore platforms and are subject to failures. We consider dynamic tasks where the timing attributes vary from one period to another. Our setting also allows for sporadic deadline overruns and accounts for criticality during fault handling. A user interface was created to allow automatic generation of the models as well as visualization of the analysis results, whereas predictability is verified using the Spin model checker.